| FEATURES PROVIDED | HERMETICALLY SEALED AND PROGRAMMABLE AND PROGRAMMED AND 3-STATE OUTPUT AND W/ENABLE AND BIPOLAR |
| INCLOSURE MATERIAL | SILICON |
| TEST DATA DOCUMENT | 82577-3542300 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| INPUT CIRCUIT PATTERN | 10 INPUT |
| MEMORY DEVICE TYPE | ROM |
| BODY WIDTH | 0.240 INCHES MINIMUM AND 0.325 INCHES MAXIMUM |
| BODY HEIGHT | 0.085 INCHES MAXIMUM |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 16 FLAT LEADS |
| INCLOSURE CONFIGURATION | FLAT PACK |
| STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MEMORY CAPACITY | UNKNOWN |
| BODY LENGTH | 0.440 INCHES MAXIMUM |
| TIME RATING PER CHACTERISTIC | 10.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 10.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |