BODY HEIGHT | 0.045 INCHES MINIMUM AND 0.085 INCHES MAXIMUM |
BODY LENGTH | 0.390 INCHES MAXIMUM |
BODY WIDTH | 0.235 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, MASTER SLAVE |
FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND W/CLEAR AND W/ENABLE AND LOW POWER |
INCLOSURE CONFIGURATION | FLAT PACK |
INCLOSURE MATERIAL | CERAMIC AND GLASS |
INPUT CIRCUIT PATTERN | DUAL 4 INPUT |
MAXIMUM POWER DISSIPATION RATING | 90.0 MILLIWATTS |
OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
TERMINAL SURFACE TREATMENT | SOLDER |
TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
TEST DATA DOCUMENT | 88818-A574A015 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
TIME RATING PER CHACTERISTIC | 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 15.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |